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NUS6160MN
Operational Description
The NUS6160 provides overvoltage protection for
positive voltages up to 20 V. A P ? Channel FET protects the
load connected on the V out pin, against positive overvoltage
conditions. The Output follows the V BUS level until OVLO
threshold is reached.
Undervoltage Lockout (UVLO)
To ensure proper operation under all conditions, the
device has a built ? in undervoltage lock out (UVLO) circuit.
As the input ramps from 0 V, the output remains
disconnected from input until the V in voltage is above 3.2 V
nominal. The FLAG output is pulled to low as long as V in
in the event of an overvoltage condition to protect the output
from a positive overvoltage condition. The low R ds(on) ,
during normal operation will minimize the voltage drop
across the device. (See Figure 16).
ESD Tests
The NUS6160 meets the requirements of the
IEC61000 * 4 * 2, level 4 (Input pin, 1 m F mounted on
board). For the air discharge condition, V in is protected up
to $ 15 kV. In the contact condition, V in is protected up to
± 8 kV ESD. Please refer to Figure 29 to see the IEC
61000 ? 4 ? 2 electrostatic discharge waveform.
does not reach the UVLO threshold. This circuit
incorporates hysteresis on the UVLO pin to provide noise
immunity to transient condition.
Figure 29. IEC 61000 ? 4 ? 2 Curve
Figure 28. Output Characteristic vs. V in
Overvoltage Lockout (OVLO)
To protect connected systems on V out Pin from
overvoltage, the device has a built ? in overvoltage lock out
(OVLO) circuit. During an overvoltage condition, the
output remains disabled until the input voltage is reduced to
below the OVLO hysteresis level. The FLAG output is tied
to low until V in is higher than OVLO. This circuit
incorporates hysteresis on the OVLO pin to provide noise
immunity from transient conditions.
FLAG Output
The NUS6160 provides a FLAG output, which alerts
external systems that a fault has occurred. This pin goes low
as soon as the OVLO threshold is exceeded. When V in level
recovers to its normal range the FLAG is set high.
The FLAG Pin is an open drain output, thus a pullup
resistor (typically 1 M W ? Minimum 10 k W ) must be
provided to V battery .
EN Input
To enable normal operation, the EN pin shall be forced
low or connected to ground. A high level on the pin
disconnects the OUT Pin from IN Pin. EN does not override
an OVLO or UVLO fault.
Internal PMOS FET
The NUS6160 includes an internal PMOS FET which
Thermal Impedance
Due to cross heating of the three dice in the package, the
equivalent thetas are given for this device rather than the
individual thetas. To calculate the junction temperatures of
a single die, the total power must be used. For example,
given the following parameters, the die temperatures will be
as shown:
I dc = 500 mA
R DS(on) OVP = 305 m W
R DS(on) FETsw = 72 m W
FET reg has a 1.0 V Drop
Board copper area = 161 mm 2
Calculate the individual power dissipations:
P OVP = (0.50 A) 2 x .305 W = 0.076 W
P SW = (0.50 A) 2 x .072 W = 0.018 W
P REG = 0.50 A x 1.0 V = 0.50 W
P TOT = 0.076 + 0.018 + 0.50 = 0.594 W
From the Maximum ratings table for thetas, 161 mm 2 and
1 V drop across FET REG :
OVP FET 53 ° C/W
FET SW 49 ° C/W
FET REG 92 ° C/W
The die temperature rises above ambient are:
T OVP = 53 ° C/W x 0.594 W = 32 ° C
T SW = 49 ° C/W x 0.594 W = 29 ° C
T REG = 92 ° C/W x 0.594 W = 55 ° C
connects the input to the output pin. This FET is turned off
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